Verilog is the first standard hardware description language that CvSDL supports. Verilog files are translated into CvSDL files by the HDL to CvSDL translator, hdl2cvsdl, which are compiled by a user-supplied C++ compiler.
The traditional Verilog-based design methodology is supported, namely that you capture design in Verilog, simulate it and debug it using a waveform viewer.
CvSDL also takes the design methodology to the next level by providing a mechanism that enables your design to be part of the C/C++/SystemC software development or C++/SystemC-based validation/verification environment for software-hardware codevelopment from early stages of development.
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