Standard Compliance

1 Summary of Unsupported IEEE Std 1364 Features

The IEEE Std 1364-2001 (the standard) is the latest Verilog standard CvSDL supports. The list below summarizes all the standard features that are not supported by the CvSDL simulator and/or the Verilog to CvSDL translator.

• Switch level features such as charge strength, trireg, CMOS switches, etc. are not supported.

• The vectored and scalared keywords and their associated features are not supported.

• Wired-logic nets are not supported as array elements.

• Delays are parsed and reduced to single delay quantities by averaging constituent delay numbers.

• Ambiguous signal strength and the strength range notation in the format string for the display system tasks are not supported.

• User-defined primitives (UDPs) are not supported.

• Procedural continuous assignments are not supported.

• Design configuration features are not supported.

• Specify blocks, specify timing check and SDF features are not supported.

• PLA modeling system tasks are not supported.

• Extended VCD format is not supported.

• The following compiler directives are ignored: `celldefine, `endcelldefine, `default_nettype, `resetall, `line, `unconnected_drive and `nounconnected_drive.

• PLI (TF/ACC/VPI) is not supported.

Note that there are some features that are supported but not working in the current version of CvSDL, and that some in the above list may be supported in the future. Also that a Verilog feature is not natively supported by CvSDL does not necessarily mean that the feature is not supported. For example, CvSDL does not support declaration-assignments except for parameters, but the translator splits such a declaration-assignment as two separate CvSDL statements.

The sections that follow detail the syntactical differences between the standard and CvSDL.

2 Lexical Elements

2.1 White space

Verilog white spaces are blank spaces, tabs, new lines and formfeeds. CvSDL uses isspace() to detect white spaces.

2.2 Comments

One-line comments (//) and block comments ( /* ... */) are supported. Note that Verilog does not allow block comments to be nested.

2.3 Numbers

2.3.1 Integer Constants

2.3.1.1 Simple Decimal Numbers

A simple Verilog decimal number is an unsigned number with zero or more underscore characters '_' inserted anywhere except at the beginning and optionally preceded by a + or – operator. The simple decimal numbers are treated as signed integers.

To use them in CvSDL, enclose them in double quotes, “”. You can also use C++ integer, int, without double quotes. C++ unsigned integer types are not supported.

CvSDL uses a 32-bit vector to represent a simple decimal number. If a constant does not fit in a 32-bit vector, the contents of the vector would be unknown.

2.3.1.2 Sized Constants

CvSDL supports Verilog sized constants fully but they must be enclosed by double quotes. If the most significant bit of an unsized unsigned constant is x or z, the value is extended to the size of the expression that contains the constant (a Verilog-2001, not Verilog-95, rule).

2.3.2 Real Constants

Verilog real constants are fully supported but they must be enclosed in double quotes; if you do not need to use the underscore characters '_', you can also use C++ double constants without double quotes.

Note that there are a few syntactical differences between Verilog and C++ double constants. For example, .12 is illegal in Verilog but it is legal in C++. You can use any legal C++ double constants with or with double quotes. Assigning a real to an integer variable will round the real to the nearest integer.

2.4 String Constants

Verilog string constants are not 0-terminated strings, but C++ 0-terminated strings can in general be used where string constants are desired. When you need to embed '\0' in a string, you need to use a sized string constant format (not a Verilog construct) that specifies the exact number of bits, which should be a multiple of 8, followed by 'sa, 'sA, 'Sa or 'SA, and finally by the desired array of characters. Strings are treated as unsigned integer. Special characters allowed in strings are \n, \t, \\, \", and the octal escape sequence \ddd. Do not use other special characters allowed in C++ to be compatible with Verilog. If the string you desire looks like a sized constant number, precede it with 'a or 'A.

2.5 Names

2.5.1 Identifiers

CvSDL requires variables to be declared as module (class/struct) members and then to be specified in terms of variable types and other attributes in the module constructor. When you specify a variable you also need to give the instance name (a 0-terminated C++ string) for the variable. The instance names, not the variable names, correspond to the Verilog variable names.

Escaped identifiers require two backslash characters (\\) in CvSDL and they are not considered to be part of the identifiers. For example, “\\net$123” and “net$123” are considered the same name as in Verilog.

Generated identifiers are also supported, but you have to manually specify how to generate the names in generate loops to match Verilog generated identifiers.

Note that, though the Verilog identifiers can be as long as 1024 characters and C++ does not impose any length limit, other tools such as assemblers and linkers may impose shorter limitations. CvSDL does not check the length of instance names.

2.5.2 Keywords

The table below summarizes all the Verilog-2001 keywords and corresponding CvSDL keywords/others. The entry '-' means there is no corresponding keyword. All the CvSDL keywords are explained in subsequent sections.

Note that the C++ keywords are also reserve.

2.5.3 System Tasks and Functions

The dollar sign ($) that starts a Verilog system task/function name is replaced by the three character sequence, cv_. For example $display() becomes cv_display().

2.5.4 Compiler Directives

Many of Verilog compiler directives have equivalent directives in C++.

2.6 Attributes

Verilog attributes should be embedded in block comments (/**/).

For example, /*(* full_case=1, parallel_case=1 *)*/.

CvSDL does not make use of them; however, they are recognized during CvSDL-to-Verilog translation.

3 Variable Types

3.1 Data Types

The two Verilog data types are both supported; 4-value logic (0,1,x,z) and real. When a real number is converted to a logic number, the real number is rounded, not truncated, to the nearest whole number per Verilog. When a logic value is converted to a real number, any x or z bits are treated as 0. No overflow check is done.

3.2 Nets, Variables, Named Events

TCvVar variables that are declared in module definitions must be specified in their constructors in CvSDL. Verilog net types (wire, tri, wand, and wor), variable types (reg, integer, real, time, and realtime), and named events are supported. The Verilog types, tri1, tri0 and trireg types are not supported.

The table below summarizes the Verilog net and variable types and CvSDL TCvVar member functions you call to specify types in CvSDL with examples.

Note that in Verilog the pairs, wire and tri, wand and triand, wor and trior, and real and realtime, are synonymous to each other.

The following Verilog features are not supported:

• implicit declarations

• vectored/scalared keywords

• net declaration assignments

3.2.1 Vectors

The maximum vector length is 65535 bits in CvSDL.

3.2.2 Charge Strength - not supported

3.2.3 Drive Strength

The drive strengths are fixed at strong levels for assignments and variable specifications. Multiple drive strengths are supported for primitive gates and pulls.

3.2.4 Specifying Types

Each TCvVar variable declared in a module definition needs to be specified in terms of its actual (Verilog-compatible) type in the constructor by calling one of the type-specifying member functions:

Both the msb and lsb must be constant expressions that resolve to integer quantities. They can be negative. If msb>lsb then the variable is little-endian; otherwise it is big-endian. The range applies only to the net (wire, tri, wand, and wor) and reg types.

The time variables are implemented as 64-bit unsigned vectors in the little-endian format with the lsb set to 0.

3.3 Arrays

There are two ways to create array variables in CvSDL.

You can create arrays using the C++ array creation mechanism:

Note the arrays created this way are translated into individual variables in Verilog.

The other way is to declare a TCvVar variable and specify it to be an array:

The specification uses a function template. The template requires the array dimension, dim, that can be up to 15. The range values, lhv and rhv, must be integer constants and can be negative. There must be as many ranges as the array dimension.

The following data types are currently not supported as array element types, tri, wand, wor, tri0, tri1, and trireg.

3.4 Parameters

3.4.1 Module Parameters

A TCvVar variable declared in a module definition can be specified as a parameter or local parameter by calling one of the (local) parameter specification functions in the constructor. These functions are TCvVar member functions.

3.4.2 Specify Parameters – not supported

3.5 Name Spaces

CvSDL is C++ and therefore C++ name spaces apply to all of CvSDL names. In addition the instance names given to CvSDL design objects are subject to the Verilog name spaces if the design should be translated to Verilog. Verilog name spaces are:

• definition name space – module, macromodule and primitive names (global)

• text macro name space – compiler directive defines (global)

• block name space – names within each of named blocks, functions, and tasks

• module name space – names within each of modules, macromodules, and primitives

• port name space – port names per each of modules, macromodules, primitives, functions and tasks (overlapping the module/block name spaces)

• specify block name space – not supported

• attribute name space – names within attributes

4 Expressions

4.1 Operators

4.1.1 Arithmetic Left Shift Operator

The arithmetic left shift operator in CvSDL is the same as logical left shift operator.

4.1.2 Conditional Operator

The Verilog conditional operator evaluates differently from the C++ conditional operator when the first expression e1 results in x or z and/or the sizes of e2 and e3 are different. The CvSDL function, cv_cond(), supports the Verilog conditional.

4.2 Operands

A valid CvSDL (and Verilog) operand is one of the following:

• Number

• Variable (a module or temporary variable excluding events)

• Bit-select or part-select of a logic variable

• Array element

• Function call that returns any of the above

A concatenation of above operands is also treated as an operand.

4.2.1 Vector Bit/Part-Select Addressing

There are one bit selection and three part selection mechanisms in Verilog-2001:

4.2.2 Array Addressing

Array elements are addressed in the same way in Verilog and CvSDL.

4.2.3 String Operands

C++ null string (“”) can be used just as in Verilog. It is equivalent to “\0”. Note that Verilog strings are not the same as C++ 0-terminated strings and may contain '\0'. See the section on String Constants on how to embed 0s in CvSDL strings.

4.3 Minimum, typical, and maximum delay expressions – not supported

4.4 Controlling the sign of an expression

4.5 Evaluation Order of an Expression

Verilog basically requires the following steps:

1. determine the expression type (implicit type conversion towards larger or real type)

2. if the type is bit-vector/logic, determine the expression bit size

3. force all operands (except for self-determined) to the type and, if the type is logic, do x, z or sign extension as needed for each operand

4. evaluate

5 Scheduling Semantics

The CvSDL Simulator is based on the Verilog simulation reference model described in the IEEE Std 1364-2001 documentation.

5.1 Simulation Cycles

A simulation cycle at time T consists of the the following steps:

1. Activate all inactive events (initials at time 0, delayed and callback processes) at T.

2. If there is an evaluation event (scheduled process), evaluate the process and schedule update events (updates of nets and variables with their values changed).

3. If there are update events, update all modified variables, schedule sensitive processes and go back to Step 2.

4. If there are (new) inactive events, go back to Step 1.

5. If there are nonblocking assign update events, activate all nonblocking assignments and go back to Step 3.

6. If there are monitor events, execute all monitor events.

7. If there is no more event scheduled in the future, DONE.

8. Advance the simulation time to the nearest future time T with a valid event.

Note that an explicit zero delay (#0 in Verilog, cv_delay(0) in CvSDL) causes the calling process to be suspended and linked to the inactive event queue.

A delta cycle may start at Step 1 or at the transition from Step 5 to Step 3 and it may end at Step 5 (that leads to Step 3) or Step 7.

5.2 Determinism

• Sequential execution of statements in procedural process – fully supported

• Multiple nonblocking assignments in a procedural block – supported.
  If there is more than one nonblocking assignment to a variable in a procedural process, CvSDL schedules only the last assignment. Verilog requires that all of the assignments be queued and executed one by one in the order that the assignments are encountered. The consequence is that the potential glitches for a variable that can be created in Verilog cannot be seen in CvSDL.

5.3 Nondeterminism

Nondeterminism exists in CvSDL as in Verilog due to the unpredictable order of executing evaluation and update events. Another source of nondeterminism in Verilog, due to possible preemptive interruptions while executing behavioral statements, does not exist in CvSDL.

5.4 Race Conditions

Race conditions are possible if you try to use the contents of a variable in one process that is being updated in another process at the same simulation time.

5.5 Scheduling Implication of Assignments

Verilog task and function arguments are passed by value using blocking assignments. CvSDL task and function arguments are passed by reference and therefore no blocking assignments take place unless temporary variables to receive arguments.

5.5.1 Switch Processing – not supported

6 Assignments

Net declaration assignments are not supported. Variable declaration assignments are not supported. Procedural continuous assignments are not supported.

Delays are supported for continuous assignments and procedural blocking and nonblocking assignments.

7 Gate Level Modeling

All Verilog primitive gates are supported in the following syntax:

cv_gate(gate_type, output, input);
cv_gate(gate_type, strength_a, strength_b, output, input);

as summarized in the table below:

Arrays of primitive gates using ranges are not supported. Generate facility should be used to generate arrays of primitive gates and modules instead. Propagation delays are not supported.

Drive strengths for the enabled gates (bufif0, bufif1, notif0 and notif1) and pulldown and pullup gates are fully supported. Drive strengths for other gate types are set to the strong 0 and strong 1.

Individual gates can be instantiated as summarized below:

The default drive strengths for pull gates are the weak0 and weak1. The default drive strengths for other gates are the strong 0 and strong 1.

8 Switch Level Modeling – not supported

9 User-Defined Primitives (UDPs) - not supported

10 Behavioral Modeling

10.1 Conditional Statement (if-else)

10.2 Case Statements

The syntactical differences for case statements between Verilog and CvSDL are:

The keywords, casev, casez, casex, case_item and case_default, are implemented as macros.

The case_default statement is optional and, if used, must appear only once as the last item in a case statement. Note the Verilog keyword 'case' is replaced by 'casev' in CvSDL. The argument to the case expression can be a constant.

Multiple expressions for a case item allowed in Verilog are not supported by the case macros. However they can be supported by modifying the case_item macro to include multiple expressions.

10.3 Looping Statements

The syntactical differences for loops statements between Verilog and CvSDL are:

10.4 Procedural Timing Controls

10.4.1 Delay Control

The delay control in CvSDL is a statement.

10.4.2 Event Control

The event control in CvSDL is a statement. Verilog @* and @(*) are not supported. Verilog-2001 allows use of ',' in place of event 'or'.

10.4.3 Named Events and Event or Operator

Named events are TCvVar variables that are specified as events. Use the comma instead of the 'event or' in CvSDL.

10.4.4 Level-Sensitive Event Control

The level-sensitive event control in CvSDL is a statement by itself.

10.4.5 Intra-Assignment Timing Controls

Verilog '@*' and '@(*)' are not supported in CvSDL. Only single-value delays are supported (no min:typ:max delay values).

10.5 Block Statements

10.5.1 Parallel (fork-join) Blocks

10.5.2 Sequential Blocks

The identifiers for Verilog named blocks are not supported except for named processes in CvSDL.

11 Structured Procedures

11.1 initial Construct

A module member function of the type

void func-name(void);

can be used as the argument to the macro initial to create a thread process that is equivalent to the Verilog initial block. The default stack size (in bytes) is specified by the constant, CV_DEFAULT_STACK_SIZE, defined in cv_types.h. If you need to change the stack size, use the macro, initial-s, instead that takes a new stack size as the second argument.

11.2 always Construct

A module member function of the type

void func-name(void);

can be used as the argument to the macro always to create a nonthread process that is equivalent to a Verilog always block of the form:

always @( event-expression )

The macro takes two arguments; the first one is the process function name and the second one is the sensitivity list.

If you need to use an indexed always process (in generate loops) you can use another macro, always_i1, that takes one integer index as an argument. The process function for the macro takes the index as the argument:

void f(int)

11.3 Tasks and Functions

CvSDL tasks and functions are simply module member functions. They follow the same distinctions made by Verilog:

• a function returns a value, but a task does not,

• a function cannot contain delay controls and event expressions, but a task can,

• a function must return a value (TCvVar), but a task must not,

• a function can call functions but cannot call tasks; a task can call functions and tasks,

• a function must have at least one input port and no outputs/inouts; a task can have zero or more ports of any type.

CvSDL tasks and functions cannot be given instance names and are always of the automatic (reentrant) type as defined in Verilog-2001. Note that synthesizable tasks and functions must be of the automatic type, per IEEE Std 1364.1-2002 and that automatic task items are accessible as defined in Verilog-2001.

Note that Verilog does not allow use of nonblocking assignments with or without a delay control or event expression and use of system tasks such as cv_monitor(), cv_dumpvars(), etc.

Formal arguments to tasks and functions must be the reference type, TCvVar&. Any expression can be used as actual arguments. Only the lvalues for procedural assignments can be connected to output arguments.

The use of the C++ keyword static for local variables to create a static task is not recommended, since they are not equivalent to Verilog static variables that are not global.

If you want to make sure the type of an input port is what you expect, you can use a temporary variable with the type and assign the input port value to the temporary..

11.4 Returning a Value from a Function

CvSDL reserves the name, cv_rval, for the function return value. Language translators will recognize its type as the function return type. You need to declare it as a temporary variable of the type and bit size, if applicable, for the function. You need to assign a value before the function is exited with the statement:

return cv_rval;

11.5 Use of Constant Functions

Constant function calls are used during elaboration time in Verilog and module construction time in CvSDL.

In order for CvSDL constant functions to be translatable to the equivalent functions in Verilog, you need to follow all the Verilog rules on them. Basically a constant function is static and not generated in generate blocks, takes only constant expressions as the arguments, ignores any system tasks, does not allow any system function calls, has all references defined locally beforehand within the current module (except for parameters, but defparams are not allowed to affect them) and does not call other constant functions.

12 Disabling of Named Blocks and Tasks

The table below summarizes the valid ways of disabling named blocks and tasks in CvSDL. Other ways not in the table, but allowed in Verilog are not supported. Note that the synthesizable Verilog only allows disabling a named block from within.

You can disable initials and threaded always that are blocked and waiting for some events or delays. When you disable an initial, the process will be disabled for the rest of the simulation. When you disable a threaded always, its stack is reinitialized and the process is queued as an inactive event.

13 Hierarchical Structures

13.1 Modules

13.1.1 Top-Level Modules

In Verilog, top-level modules do not need to be instantiated, but in CvSDL they must be instantiated and registered through TCvSdl::RegisterComponent(). They are then maintained as sub-modules of the internal (not user-defined) top level module called “CvSDL”.

13.1.2 Module Instantiation

Arrays of instances (using the range specification) are not supported. If you want to generate module arrays, use the generate facility instead.

Blank port connections are not supported except for default parameter ports at the end of a port list. Port connections by name are not supported.

To instantiate a module in CvSDL, use the instance macro, the only argument to which is the module constructor with actual arguments.

13.1.3 Generated Instantiation

The generate facility is supported in module constructors. You can specify variables or generate multiple instances of one or more of the following objects in loops using the for-loop statement or conditionally using the if-else statement or the case statements:

• modules

• primitive gates

• continuous assignments

• initial processes

• always processes

UDPs are not supported.

In Verilog, tasks and functions can be generated conditionally but not in loops. In CvSDL, tasks and functions cannot be generated in generate blocks; instead of generating tasks and functions in generate blocks, you can simply include conditionals inside tasks and functions. You could, though considered not translatable currently, use a function pointer to conditionally point to a desired function.

No variables can be declared inside generate blocks; they must be declared as module variables beforehand. But they can be specified in generate blocks. Specified variables and generated instances can be uniquely named and referenced hierarchically.

Unlike defparam statements in generate blocks in Verilog, defparam statements in CvSDL are not limited to the generate blocks that include them. That is, there is no scope limitation in CvSDL as there is in Verilog.

13.1.3.1 genvar - generate statement index variable

Any integer variables defined in the module constructor and used in generate blocks are considered genvars.

13.1.3.2 Generate-Loop

13.1.3.3 Generate-Conditional

13.1.3.4 Generate-Case

13.2 Overriding Module Parameter Values

There are three ways to override default parameter values:

• defparam statement – supported

• module instance parameter value assignment by ordered list – supported

• module instance parameter value assignment by name – not supported

13.2.1 defparam Statement

The defparam statement overriding a parameter must appear before the module that contains the parameter during compilation. If there is more than one defparam statement for a parameter, a warning is generated and the last statement encountered, before the parameter is elaborated, is used to override the default value of the parameter.

13.2.2 Parameter Value Assignment by Ordered List

The Verilog parameter value assignment by ordered list uses the C++ function arguments with default initialization values.

13.2.3 Parameter Dependence

Overridden values for parameters are propagated to others that are dependent on the parameters.

13.3 Ports

The following features are not directly supported:

• List of ports declarations in Verilog-2001 - not supported

• Connecting module instance ports by name - not supported

13.3.1 List of Ports

The list of ports or the module ports are the formal arguments to the constructor of a module that are declared as TCvVar references, TCvVar&.

13.3.2 Port Specification/Binding

Note that ports must be specified one variable at a time.

port-specification:
port-type ( inst-name, local-var, port-var ) ;
port-type ( inst-name, local-var, range, port-var ) ;

port-type: one of
input output inout

13.3.3 Connecting Module Instance Ports by Ordered List

Any valid expression can be connected to each port of a module.

13.3.4 Real Numbers in Port Connections

Use cv_realtobits() and cv_bitstoreal() to pass reals as bits across module ports.

13.3.5 Port Connection Rules

Each port connection behaves as a continuous assignment to the lvalue.

An input or inout port must be a valid lvalue for continuous assignments.

Input ports that are assigned values internally (used as outputs) are considered fatal errors in CvSDL; they generate warning messages in Verilog.

13.3.6 Connecting Dissimilar Data Types at Ports - not supported

The synthesizable subset of Verilog ignores the net types resulting from connecting dissimilar data types at ports that are defined in Verilog-2001, potentially causing simulation mismatches between RTL and gate level models. CvSDL allows the connections of truly compatible data types only.

The table below summarizes the compatible internal and external data types at ports. The entries with '-' indicate the combinations of the corresponding data types are not allowed and error messages will be generated.

13.3.7 Connecting Signed Values via Ports

In CvSDL, sub-module ports assume the signs of the expressions connected to the ports. The use of signed types across ports should be avoided unless the signs are used consistently across ports (no sign conversions).

13.4 Hierarchical Names

The hierarchical path names in CvSDL are formed in the same manner as in Verilog but enclosed in double quotes (“”).

13.5 Upwards Name Referencing

Searching for a hierarchical name starts with

• a module identifier (module-identifier.item-name), or

• a module instance name (module-instance-name.item-name)

The search algorithm is specified by Verilog. Note that module-instance-name is searched first before module-identifier at the current level.

A valid item-name is the name of a net, a variable, a parameter or named block. Functions and tasks are automatic and their internal objects are not accessible.

Use the following two functions, cv_variable() and cv_block(), to get references to named objects:

hierarchical-variable-reference:
cv_variable ( “ hierarchical-variable-path-name “ )

hierarchical-block-reference:
cv_block ( “ hierarchical-block-path-name “ )

cv_variable() returns the reference to a variable. If the variable does not exist, the reference is to a dummy variable and a warning message is generated.

cv_block() returns the reference to a block such as a process or module. If the block does not exist, it return the reference to the “CvSDL” module and a warning message is generated.

13.6 Scope Rules

CvSDL uses the C++ scope rules that are basically the same as the Verilog scope rules. However when an object is given a string name, the string name (not the object name recognized by C++) actually corresponds to the equivalent Verilog name. Therefore you need to make sure string names do not collide within the same scope.

If a task or function is referenced directly in a module, it must be a module member task or function in CvSDL, whereas Verilog allows the use of a task or function defined in a higher-level module.

14 Configuring the Contents of a Design – not supported

15 Specify Blocks – not supported

16 Timing Checks – not supported

17 Backannotation Using SDF – not supported

18 System Tasks and Functions

All Verilog system tasks and functions, except for PLA modeling tasks, are supported. The dollar sign ($) in front of a name is replaced by “cv_”. For example, $display() becomes cv_display(). Arguments to some tasks and functions are slightly different from Verilog. The differences are noted below.

You can use C++ file I/O functions for some of Verilog file I/O functions such as ftell().

18.1 Display System Tasks

The item not supported is the format specification, %l and %L, for displaying library binding information. Also note that CvSDL does not support charge strengths.

18.2 File Input-Output System Tasks and Functions

18.3 Timescale System Tasks

18.4 Simulation Control System Tasks

18.5 PLA Modeling System Tasks – not supported

18.6 Stochastic Analysis Tasks

18.7 Simulation Time System Functions

18.8 Conversion Functions

18.9 Probabilistic Distribution Functions

18.10 Command Line Input

19 Value Change Dump (VCD) Files

19.1 4-Value VCD Files

The dumpvars() argument list, list-of-mods-or-vars, are translated to an appropriate cv_dumpvars() statement for each item in the list.

19.2 Extended VCD Files – not supported

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Copyright © 2005 Tenko Technologies Inc. All rights reserved. Last modified on 08/14/05.