The basic steps you need to follow to simulate your Verilog design are:
download environment-specific files from our download page.
place those files with your design files in a directory.
you can either compile a open-source script (cvsdl.cpp) to make sure you can compile anything at all in the environment you have or use the precompiled script, cvsdl/cvsdl.exe to run simulation.
Once you understand what needs to be done, you can customize the steps as you like; cvsdl.cpp describes the basic steps of translating your Verilog models, compiling them and running simulation.
You need to download the following files:
cv_types.h
libcvsdl_g323.so
hdl2cvsdl
either/both executable cvsdl or open-source cvsdl.cpp
If you downloaded cvsdl.cpp, just compile it to create the executable cvsdl:
% g++ -o cvsdl cvsdl.cpp
Then run cvsdl to translate, compile and simulate your Verilog files (add g++ options as you fit in cvsdl.cpp):
% cvsdl <your_Verilog_files> // e.g. cvsdl my_design.v
If the directory you are using is executable and in the PATH, the simulation should starts. If you need to keep the library file in a separate directory, you can use the -L flag to specify the directory. Run cvsdl with no argument for help.
If you have enabled the VCD dump, you can use a waveform view such as gtkwave to aid in debugging your design.
We have used gcc 3.2.3 on Redhat Enterprise Linux WS (v3) for our tools development.
You need to download the following files (bcb6 files are for Borland C++Builder 6 and vc7 files are for Microsoft Visual C++ 7/8):
cv_types.h
link library: either cvsdl_bcb6.lib or cvsdl_vc7.lib
run-time library: either cvsdl_bcb6.dll or cvsdl_vc7.dll
hdl2cvsdl.exe
either/both executable cvsdl.exe or open-source cvsdl.cpp
optionally, winvcd.exe
If you downloaded cvsdl.cpp, just compile it to create the executable, cvsdl.exe, Type for Borland compiler (the directory C:\cvsdl is arbitrary) in the Command Prompt window:
C:\cvsdl> bcc32 cvsdl.cpp
or for Microsoft compiler
C:\cvsdl> cl /EHsc cvsdl.cpp
Then type in the Command Prompt window:
C:\cvsdl> cvsdl -bcc <your_Verilog_files> // e.g. cvsdl -bcc my_design.v for Borland BCB 6
or
C:\cvsdl> cvsdl -vc <your_Verilog_files> // e.g. cvsdl -vc my_design.v for MS VC7
If you have enabled the VCD dump, you can use a waveform viewer such as winvcd.exe or gtkwave to aid in debugging your design.
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© 2005 Tenko
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