Experienced hardware engineers working on systems involving hardware and software typically know what software should do and what hardware should provide in terms of CPUs, dedicated processors, interrupts, data-transfer structures, memory subsystems, system-wide data coherency, peripheral devices, power cycles, and the like. CvSDL is a tool to concretize these initial ideas early in projects as executable specifications that can be written in Verilog on the hardware side and in C++ on the software side.
You may have been trained to use Verilog only in synthesizable coding styles for 'real' models and occasionally in behavioral styles for testbenches and therefore are under the impression that Verilog is only good for low-level coding and slow with those real models. But you can actually write fast high-level models using Verilog, that are realistic at early development stages.
A high-level design can be characterized by simple communication among functional modules, which may contain just algorithms, detailed models such as system power state control logic, etc. It is almost customary to use C/C++ to describe algorithms. But Verilog being C like, it can also describe those algorithms, if they are synthesizable at all to RTL. The main reason why Verilog is not used for algorithmic-level modeling is because there is no easy way to connect the models with software applications and/or testbenches that are typically written in C/C++. CvSDL automatically generates C++ codes for algorithms written in Verilog.
A communication link can be thought of as a message route, which, In Verilog, is a vector net and nothing more. For example, the entire PCI-bus master and target logic blocks could be replaced by a vector net, since at a level of abstraction it really would not matter how messages are passed through the route. A high-speed link may require pipelined command and data streams that require two vector nets operating somewhat independently. Other nets may be added as needed, for example, to implement realistic interrupt structures, to check FIFO back-pressuring, deadlocks, etc.
A message is
typically divided into fields that are assigned to bit fields of a
vector. You can use the Verilog `define directive to assign bit
fields initially like
`define px_cmd p_msg[63:48]
`define
px_addr p_msg[48:8]
and when they need to be represented as
separate nets later on, you can redefine it as
`define px_cmd
p_cmd
`define px_addr p_addr
so that the use of `px_cmd,
`px_addr, etc. in expressions is undisturbed.
As projects progress, abstract communication links will be replaced by real modules.
To describe functions at a high level of abstraction, you can make full use of the Verilog real data type, real-type operators and other behavioral constructs to represent high-level algorithms. An untimed sequence can be realized as a series of task calls.
You can speed up Verilog models, if you
use alway blocks to describe random logic.
use continuous assignments only to describe array reads and wired logic nets that require resolution.
do not use nonblocking assignments except to describe real flipflops in edge-sensitive always blocks.
do not use any delay except to model testbench components somewhat realistically.
do not use, explicitly, any signal strengths other than the default implied except to model state holders using pulls or some special circuitry.
do not use primitive gates.
reduce the number of always and initial blocks, for example, by putting flipflops into a few always blocks instead of separate always blocks.
use low-power design techniques, such as gating off primary clocks, disabling inactive modules, etc., that result in fewer simulation events.
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CvSDL is a trademark of Tenko Technologies Inc.
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© 2005 Tenko
Technologies Inc. All rights reserved. Last modified on