Q. Is CvSDL another hardware description language standard?
No. CvSDL is a framework to bring HDL models into C++ that can be part of software development ecosystems. You can think of it as an intermediate language for HDLs.
Q. Where can I get the LRM for CvSDL?
There is no LRM for CvSDL. Although its grammar is currently based on the Verilog standard for ease of debugging hardware models in software environment, it will change without any prior notice as other standard HDLs are supported. However the API will be relatively stable and documented for the public use.
Q. Which C++ compilers are supported?
CvSDL currently supports g++ on GNU/Linux x86, and Borland BCC32/BCB 6 and VC++ .NET/CL (VC7, VC8) on Windows 2000/XP.
Q. Why does CvSDL support SystemC?
We are supporting it because it is free, is a standard (to-be), has models in public domain, supports fixed-point types and provides TLM and SCV libraries. SystemC augments CvSDL. For example, you can write hardware models in Verilog and test them using the SCV library.
Q. Where can I get static libraries?
They will be included in license subscription CDs.
Q. How is CvSDL different from other C-based tools and HDL to C tools?
CvSDL does not require Verilog users to learn any new languages that some C-based tools do. Most Verilog-to-C/C++ tools can translate only synthesizable constructs.
Q. Does CvSDL impose any limitation on application software?
No. You can embed the CvSDL simulator and hardware models into any C++ application programs. If you want software to be responsive while simulation is running, you must use a separate thread for the CvSDL simulator. The CvSDL simulator itself runs in a single thread and does not use any additional OS-managed thread.
Q. Can CvSDL work in real-time?
Yes. CvSDL models can be simulated with real hardware or at human speeds by synchronizing hardware to simulation or simulation to hardware, or simulation to host computer clock.
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CvSDL is a trademark of Tenko Technologies Inc.
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