Notes:
The latest version is 0.4.275.
The CvSDL regression test suites are not yet complete, so there may be obvious bugs that are not listed below. Please email us if you think you found a new bug.
Error reporting/handling is not very user-friendly. All fatal errors will attempt to abort simulation. Other errors and informative warnings if detected will generate warning messages, some of which might be fatal. You need to take a close look at warnings generated during elaboration time; they are often fatal.
|
Category |
ID |
Description |
Fixed in Version |
|
module port |
1 |
Complex port descriptions such as two ports short-circuited within a module or an internal port connected to multiple module ports as in bit concatenated ports are not yet supported. |
1.0 |
|
module port |
2 |
Implicit port type conversions are not yet tested except for obvious wire to tri conversions. |
1.0 |
|
disable statement |
1 |
Disable statements are not supported. |
1.0 |
|
tri1/tri0 |
1 |
hdl2cvsdl fails to generate correct CvSDL declarations |
0.5 |
|
type conversion |
1 |
Only obvious ones, inout ports and immediate value 'z' assignments, are automatically converted currently. Note that the CvSDL wire type does not cause any automatic value resolution based on the tri type, so some Verilog wires, intended to be used as tris, need to be coverted to tris in CvSDL. |
0.5 |
|
procedural continuous assignments |
1 |
Not implemented yet. |
1.0 |
|
instantiation range |
1 |
Module instantiations with range. hdl2cvsdl does not translate the range specifier currently. It ignores it. |
1.0 |
|
instantiation range |
2 |
Primitive gate instantiations with range. hdl2cvsdl does not translate the range specifier currently. It ignores it. |
1.0 |
|
automatic variables |
1 |
The automatic variables for tasks and functions introduced in Verilog-2001. hdl2cvsdl ignores the keyword 'automatic' currently and generate local variables as per-module persistent variables, compatible with the pre-2001 standard. |
0.5 |
|
continuous assignment |
1 |
Continuous assignment delays use transport delays not inertial delays. |
0.5 |
|
parsing |
1 |
Attributes introduced in Verilog-2001. Not tested at all. |
0.5 |
|
file-I/O |
1 |
Handle returned from cv_fopen() is not Verilog compatible in terms of the bit layout. |
0.5 |
|
event expression |
1 |
@* and @(*) are not supported by hdl2cvsdl. |
0.5 |
|
generate |
1 |
hdl2cvsdl does not generate correct statements. |
1.0 |
Notes:
The latest version is 0.3.1.
|
Category |
ID |
Description |
Fixed in Version |
|
winvcd.exe |
1 |
After a cut and paste of signals, clicking on black area of the waveform display panel may generate an error messages. |
0.3.2 |
|
hdl2cvsdl |
1 |
-y and -v flags may not work as expected. |
next 0.4 |
|
Category |
ID |
Description |
Fixed in Version |
|
VCD |
1 |
VCD dump code is erroneously generated. |
0.4 |
|
expression evaluation |
1 |
A number of problems including signed data types. |
0.4 |
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© 2005 Tenko
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